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74abt373a octal transparent latch (3-state) product specification 1995 feb 17 integrated circuits ic23 data handbook
philips semiconductors product specification 74abt373a octal transparent latch (3-state) 2 1995 feb 17 853-1454 14852 features ? 8-bit transparent latch ? 3-state output buffers ? output capability: +64ma/32ma ? latch-up protection exceeds 500ma per jedec std 17 ? esd protection exceeds 2000 v per mil std 883 method 3015 and 200 v per machine model ? power-up 3-state ? power-up reset ? live insertion/extraction permitted description the 74abt373a high-performance bicmos device combines low static and dynamic power dissipation with high speed and high output drive. the 74abt373a device is an octal transparent latch coupled to eight 3-state output buffers. the two sections of the device are controlled independently by enable (e) and output enable (oe ) control gates. the data on the d inputs are transferred to the latch outputs when the latch enable (e) input is high. the latch remains transparent to the data inputs while e is high, and stores the data that is present one setup time before the high-to-low enable transition. the 3-state output buffers are designed to drive heavily loaded 3-state buses, mos memories, or mos microprocessors. the active-low output enable (oe ) controls all eight 3-state buffers independent of the latch operation. when oe is low, the latched or transparent data appears at the outputs. when oe is high, the outputs are in the high-impedance aoffo state, which means they will neither drive nor load the bus. quick reference data symbol parameter conditions t amb = 25 c; gnd = 0v typical unit t plh t phl propagation delay dn to qn c l = 50pf; v cc = 5v 3.2 3.6 ns c in input capacitance v i = 0v or v cc 4 pf c out output capacitance outputs disabled; v o = 0v or v cc 7 pf i ccz total supply current outputs disabled; v cc =5.5v 100 m a ordering information packages temperature range outside north america north america dwg number 20-pin plastic dip 40 c to +85 c 74abt373a n 74abt373a n sot146-1 20-pin plastic so 40 c to +85 c 74abt373a d 74abt373a d sot163-1 20-pin plastic ssop type ii 40 c to +85 c 74abt373a db 74abtd373a b sot339-1 20-pin plastic tssop type i 40 c to +85 c 74abt373a pw 7abt373apw dh sot360-1 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 oe q0 d0 d1 q1 q2 d2 d3 q3 q4 gnd d4 d5 q5 q6 d6 d7 q7 v cc e sa00059 pin description pin number symbol function 1 oe output enable input (active-low) 3, 4, 7, 8, 13, 14, 17, 18 d0-d7 data inputs 2, 5, 6, 9, 12, 15, 16, 19 q0-q7 data outputs 11 e enable input (active-high) 10 gnd ground (0v) 20 v cc positive supply voltage
philips semiconductors product specification 74abt373a octal transparent latch (3-state) 1995 feb 17 3 logic symbol 3 4 7 8 13 14 18 17 d0 d1 d2 d3 d4 d5 d6 d7 q0 q1 q2 q3 q4 q5 q6 q7 2 5 6 9 12 15 16 19 1 11 oe e sa00060 function table inputs internal outputs operating oe e dn register q0 q7 operating mode l l h h l h l h l h enable and read register l l l h l h l h latch and read register l l x nc nc hold h h l h x dn nc dn z z disable outputs h = high voltage level h = high voltage level one set-up time prior to the high-to-low e transition l = low voltage level l = low voltage level one set-up time prior to the high-to-low e transition nc= no change x = don't care z = high impedance aoffo state = high-to-low e transition logic symbol (ieee/iec) 11 32 4 5 7 6 89 c1 13 12 14 15 17 16 18 19 1 en 1d sa00061 logic diagram e q d d0 q0 eq d d1 eq d d2 eq d d3 eq d d4 eq d d5 eq d d6 eq d d7 q1 q2 q3 q4 q5 q6 q7 e oe sa00062 3 4 7 8 13 14 17 18 11 1 2 5 6 9 12 15 16 19
philips semiconductors product specification 74abt373a octal transparent latch (3-state) 1995 feb 17 4 absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +7.0 v i ik dc input diode current v i < 0 18 ma v i dc input voltage 3 1.2 to +7.0 v i ok dc output diode current v o < 0 50 ma v out dc output voltage 3 output in off or high state 0.5 to +5.5 v i out dc output current output in low state 128 ma t stg storage temperature range 65 to 150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. recommended operating conditions symbol parameter limits unit symbol parameter min max unit v cc dc supply voltage 4.5 5.5 v v i input voltage 0 v cc v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i oh high-level output current 32 ma i ol low-level output current 64 ma d t/ d v input transition rise or fall rate 0 5 ns/v t amb operating free-air temperature range 40 +85 c
philips semiconductors product specification 74abt373a octal transparent latch (3-state) 1995 feb 17 5 dc electrical characteristics limits symbol parameter test conditions t amb = +25 c t amb = 40 c to +85 c unit min typ max min max v ik input clamp voltage v cc = 4.5v; i ik = 18ma 0.9 1.2 1.2 v v cc = 4.5v; i oh = 3ma; v i = v il or v ih 2.5 2.9 2.5 v v oh high-level output voltage v cc = 5.0v; i oh = 3ma; v i = v il or v ih 3.0 3.4 3.0 v v cc = 4.5v; i oh = 32ma; v i = v il or v ih 2.0 2.4 2.0 v v ol low-level output voltage v cc = 4.5v; i ol = 64ma; v i = v il or v ih 0.3 0.55 0.55 v v rst power-up output low voltage 3 v cc = 5.5v; i o = 1ma; v i = gnd or v cc 0.13 0.55 0.55 v i i input leakage current v cc = 5.5v; v i = gnd or 5.5v 0.01 1.0 1.0 m a i off power-off leakage current v cc = 0.0v; v o or v i 4.5v 5.0 100 100 m a i pu /i pd power-up/down 3-state output current v cc = 2.0v; v o = 0.5v; v oe = don't care v 1 = gnd or v cc 5.0 50 50 m a i ozh 3-state output high current v cc = 5.5v; v o = 2.7v; v i = v il or v ih 0.1 50 50 m a i ozl 3-state output low current v cc = 5.5v; v o = 0.5v; v i = v il or v ih 0.1 50 50 m a i cex output high leakage current v cc = 5.5v; v o = 5.5v; v i = gnd or v cc 5.0 50 50 m a i o output current 1 v cc = 5.5v; v o = 2.5v 50 100 180 50 180 ma i cch v cc = 5.5v; outputs high, v i = gnd or v cc 100 250 250 m a i ccl quiescent suppl y current v cc = 5.5v; outputs low, v i = gnd or v cc 24 30 30 ma i ccz quiescent su ly current v cc = 5.5v; outputs 3-state; v i = gnd or v cc 100 250 250 m a d i cc additional supply current per input pin 2 v cc = 5.5v; one input at 3.4v, other inputs at v cc or gnd 0.5 1.5 1.5 ma notes: 1. not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. this is the increase in supply current for each input at 3.4v. 3. for valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. ac characteristics gnd = 0v, t r = t f = 2.5ns, c l = 50pf, r l = 500 w limits symbol parameter waveform t amb = +25 o c v cc = +5.0v t amb = -40 to +85 o c v cc = +5.0v 0.5v unit min typ max min max t plh t phl propagation delay dn to qn 2 1.4 1.4 3.2 3.6 4.2 4.7 1.4 1.4 4.7 5.1 ns t plh t phl propagation delay e to qn 1 1.4 1.9 3.2 3.7 4.2 4.8 1.4 1.9 4.8 5.1 ns t pzh t pzl output enable time to high and low level 4 5 1.2 2.1 3.1 4.2 4.2 5.2 1.2 2.1 5.1 5.7 ns t phz t plz output disable time from high and low level 4 5 1.3 1.2 3.4 3.0 4.6 4.1 1.3 1.2 5.1 4.3 ns
philips semiconductors product specification 74abt373a octal transparent latch (3-state) 1995 feb 17 6 ac setup requirements gnd = 0v, t r = t f = 2.5ns, c l = 50pf, r l = 500 w limits symbol parameter waveform t amb = +25 o c v cc = +5.0v t amb = -40 to +85 o c v cc = +5.0v 0.5v unit min typ min t s (h) t s (l) setup time, high or low dn to e 3 1.5 1.0 0.7 0.4 1.5 1.0 ns t h (h) t h (l) hold time, high or low dn to e 3 1.0 1.0 0.0 0.5 1.0 1.0 ns t w (h) e pulse width high 1 2.5 1.7 2.5 ns ac waveforms v m = 1.5v, v in = gnd to 3.0v t w (h) t phl t plh e qn sa00063 v m v m v m v m v m waveform 1. propagation delay, enable to output, and enable pulse width v m v m v m v m qn dn t plh t phl sa00064 waveform 2. propagation delay for data to outputs note: the shaded areas indicate when the input is permitted to change for predictable output performance. v m dn v m v m v m v m e t s (h) t h (h) t s (l) t h (l) sa00065 v m waveform 3. data setup and hold times oe v m t pzh t phz 0v qn v m v m sa00066 v oh 0.3v waveform 4. 3-state output enable time to high level and output disable time from high level oe t pzl t plz 0v qn v m v m v m sa00067 v ol +0.3v waveform 5. 3-state output enable time to low level and output disable time from low level
philips semiconductors product specification 74abt373a octal transparent latch (3-state) 1995 feb 17 7 test circuit and waveform pulse generator r t v in v out c l r l v cc r l 7.0v test circuit for 3-state outputs v m v m t w amp (v) negative pulse 10% 10% 90% 90% 0v v m v m t w amp (v) positive pulse 90% 90% 10% 10% 0v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) v m = 1.5v input pulse definition definitions r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. input pulse requirements family amplitude rep. rate t w t r t f 74abt 3.0v 1mhz 500ns 2.5ns 2.5ns switch position test switch t plz closed t pzl closed all other open sa00012 d.u.t.
philips semiconductors product specification 74abt373a octal transparent latch (3-state) 1995 feb 17 8 dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
philips semiconductors product specification 74abt373a octal transparent latch (3-state) 1995 feb 17 9 ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1
philips semiconductors product specification 74abt373a octal transparent latch (3-state) 1995 feb 17 10 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
philips semiconductors product specification 74abt373a octal transparent latch (3-state) philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1995 all rights reserved. printed in u.s.a.

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